Equalization of signal at the front end of a receiver to compensate for channel losses is a well known phenomenon in communication systems. Equalizer which adapt and operate at various channel lengths, data rates, transmitter swing, pre-emphasis settings etc are desirable. Particularly, for high performance, an equalizer must be able to adapt to various conditions (channel length, data rates etc) at high speed as well as produce low output jitter.
Several equalization schemes have been suggested in the past, however, they fail to achieve high speed of operation. Also, such schemes of the past require high area and power consumption as well as cause high deterministic jitters. Particularly, a conventional equalizer is not able to provide optimal control code during a training period itself (i.e. with no extra timings overhead), for data rates 1.60 Gbps to 5.4 Gbps, cable lengths 10 cm to 15 feet, various transmitter swing, various pre-emphasis/de-emphasis settings and achieve less than 0.15 UI deterministic jitter (DJ) across PVT variations.
U.S. Pat. Nos. 9,049,068 and 9,059,874 recite equalization schemes but lack eye opening monitoring. Particularly, US '068 recite low pass and high pass filter in parallel to an equalizer to generate rail to rail signal. US '874 recite a switched continuous time linear equalizer with an integrated sampler having feedback equalizer. However, their mechanism involves complex topology with no eye opening monitoring circuit. Further, equalizer of these arts consumes a lot of power and area, which is not desirable in several digital electronic circuitries.
U.S. Pat. Nos. 9,319,039 and 9,397,823 relate to reduction of jitter. However, these arts do not have any eye opening monitoring and biasing mechanism to achieve high speed equalization.
US2007/0047636 and U.S. Pat. No. 9,544,170 describe high speed and adaptive equalizer respectively. Particularly, US '636 recite about high speed line equalizer and method thereof. US '170 disclose adaptive equalization working on feedback loop taking longer convergence time with more chances of error. However, US '636 is not relevant for embedded clock applications. US '170 relies on feedback mechanism and this is not able to achieve high speed adaption. Further, both these arts have no offset cancellation mechanism to achieve low deterministic jitter, as desired.
In view of the foregoing, there is a requirement of high performance equalizer functioning at high speed for adapting to various data rates, channel lengths, transmitter swings, pre-emphasis/de-emphasis settings etc. Also, it is desirable that deterministic jitters (DJ) is low from the gain stages (after the equalization) by reducing the effect of random offset accumulation.